The invention relates to an integrated memory circuit in which memory cells are arranged in columns and in which each column is connected to two bit lines, and in which, for writing information into a memory cell of a column, that memory cell can be selected by means of selection means, which selection means connect the memory cell to the two bit lines and connect the two bit lines to a data bus for supplying information to the memory cell, each of the two bit lines being connected, via a respective load, to a first supply terminal, the data bus comprising a line which supplies a signal to a first bit line, inverting means being provided per column that generate a logically complementary signal on a second bit line.
Such a memory circuit is disclosed in U.S. Pat. No. 4,133,611. In this circuit arrangement the bit of information, present on a single data supply line, is set on the bit lines of the selected column in such a manner that from the data supply line the non-inverted signal passes a first and second inverting amplifier before appearing on the first bit line, while from the same data supply line the non-inverted signal passes a third inverting amplifier before appearing on the second bit line in the inverted form (FIG. 18c). The second and third amplifiers, both constructed as tri-state amplifiers, also play the role of access gate to the column. Another prior art memory circuit having, upon selection, a direct connection between a data input and a bitline, and an inverter between the data input and a second bitline is shown in FIG. 1 of German Patent Application DE-3430144.
In the first-mentioned reference an inverting amplifier comprises at least two transistors and a tri-stage amplifier comprises at least four transistors, which amplifiers must have connections to the supply lines. This involves that between the single data supply line and the memory cells connected to the two bit lines of a column at least ten transistors are present as well as the necessary supply source connections. In order to save area on the memory IC it is desirable to restrict the number of components between data supply lines and memory cell column. Furthermore it is desirable to keep the number of connection points to the supply lines as small as possible, because said connections should be as large as possible in the lay-out for reasons of reliability.